1. Field
The disclosed embodiments generally relate to clocked memory systems. More specifically, the disclosed embodiments relate to a technique for supporting calibration for full-rate and sub-rate operation in low-power clocked memory systems.
2. Related Art
Mobile computing systems typically operate at reduced clock frequencies when computational workloads are low. These reduced clock frequencies make it possible to decrease power consumption, which can significantly extend battery life. As the clock frequency of a mobile computing system decreases, the operating frequency of an associated clocked memory system needs to decrease proportionately. In existing calibrated memory systems (such as systems using extreme data rate (XDR) or double-data rate (DDR) memory interfaces) this typically involves performing a recalibration operation to ensure that the clocked memory system continues to function optimally at the decreased operating frequency. This is particularly important because as clock frequencies are reduced, the calibration setting will change because of frequency dependent delay and jitter in the system, which creates the need for additional timing margin so that the system is correctly calibrated for data sampling during lower frequency operation. Hence, in high-speed calibrated memory systems, the bit sampling phase and word alignment settings need to be changed when the frequency changes. Note that systems which use fixed delay lines have suboptimal settings (with equal or lower timing margins) at lower operating frequencies. Unfortunately, this recalibration operation is time-consuming which can adversely affect memory system performance, and can make it less attractive to reduce clock frequencies for short periods of time.
Hence, what is needed is a technique that facilitates reducing the operating frequency of a memory system without the need to perform a time-consuming recalibration operation.